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1/34 april 2004 m93s66, m93s56 m93s46 4kbit, 2kbit and 1kbit (16-bit wide) microwire serial access eeprom with block protection features summary industry standard microwire bus single supply voltage: ? 4.5 to 5.5v for m93sx6 ? 2.5 to 5.5v for m93sx6-w ? 1.8 to 5.5v for m93sx6-r single organization: by word (x16) programming instructions that work on: word or entire memory self-timed programming cycle with auto- erase user defined write protected area page write mode (4 words) ready/busy signal during programming speed: ? 1mhz clock rate, 10ms write time (current product, identified by process identification letter f or m) ? 2mhz clock rate, 5ms write time (new product, identified by process identification letter w or g) sequential read operation enhanced esd/latch-up behavior more than 1 million erase/write cycles more than 40 year data retention figure 1. packages pdip8 (bn) 8 1 so8 (mn) 150 mil width 8 1 tssop8 (dw) 169 mil width tssop8 (ds) 3x3mm body size
m93s66, m93s56, m93s46 2/34 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. dip, so and tssop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 power-on data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. instruction set for the m93s46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 3. instruction set for the m93s66, m93s56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. read, write, wen and wds sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 write enable and write disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. pawrite and wral sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 write all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. pread, prwrite and pren sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. prclear and prds sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 write protection and the protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 protection register read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 protection register enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 protection register clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 protection register write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 protection register disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 common i/o operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. operating conditions (m93sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. operating conditions (m93sx6-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7. operating conditions (m93sx6-r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 8. ac measurement conditions (m93sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. ac measurement conditions (m93sx6-w and m93sx6-r). . . . . . . . . . . . . . . . . . . . . . . 17
3/34 m93s66, m93s56, m93s46 figure 9. ac testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 10. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11. dc characteristics (m93sx6, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 12. dc characteristics (m93sx6, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 13. dc characteristics (m93sx6-w, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 14. dc characteristics (m93sx6-w, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 15. dc characteristics (m93sx6-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 16. ac characteristics (m93sx6, device grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 17. ac characteristics (m93sx6-w, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 18. ac characteristics (m93sx6-w, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 19. ac characteristics (m93sx6-r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10.synchronous timing (start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11.synchronous timing (read or write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12.synchronous timing (read or write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13.pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package outline . . . . . . . . . . . . . . . . . 28 table 20. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package mechanical data . . . . . . . . . . 28 figure 14.so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline . . . . 29 table 21. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data 29 figure 15.tssop8 3x3mm2 ? 8 lead thin shrink small outline, 3x3mm2 body size, package outline 30 table 22. tssop8 3x3mm2 ? 8 lead thin shrink small outline, 3x3mm2 body size, mechanical data 30 figure 16.tssop8 ? 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . 31 table 23. tssop8 ? 8 lead thin shrink small outline, package mechanical data . . . . . . . . . . . . 31 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 24. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 table 25. how to identify current and new products by the process identification letter . . . . . . . 32 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 26. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
m93s66, m93s56, m93s46 4/34 summary description this specification covers a range of 4k, 2k, 1k bit serial electrically erasable programmable memo- ry (eeprom) products (respectively for m93s66, m93s56, m93s46). in this text, these products are collectively referred to as m93sx6. figure 2. logic diagram table 1. signal names the m93sx6 is accessed through a serial input (d) and output (q) using the microwire bus proto- col. the memory is divided into 256, 128, 64 x16 bit words (respectively for m93s66, m93s56, m93s46). the m93sx6 is accessed by a set of instructions which includes read, write, page write, write all and instructions used to set the memory protec- tion. these are summarized in table 2. and table 3. ). a read data from memory (read) instruction loads the address of the first word to be read into an internal address pointer. the data contained at this address is then clocked out serially. the ad- dress pointer is automatically incremented after the data is output and, if the chip select input (s) is held high, the m93sx6 can output a sequential stream of data words. in this way, the memory can be read as a data stream from 16 to 4096 bits (for the m93s66), or continuously as the address counter automatically rolls over to 00h when the highest address is reached. within the time requir ed by a programming cycle (t w ), up to 4 words may be written with help of the page write instruction. the whole memory may also be erased, or set to a predetermined pattern, by using the write all instruction. within the memory, a user defined area may be protected against further write instructions. the size of this area is defined by the content of a pro- tection register, located outside of the memory ar- ray. as a final protection step, data may be permanently protected by programming a one time programming bit (otp bit) which locks the protection register content. programming is internally self-timed (the external clock signal on serial clock (c) may be stopped or left running after the start of a write cycle) and does not require an erase cycle prior to the write instruction. the write instruction writes 16 bits at a time into one of the word locations of the m93sx6, the page write instruction writes up to 4 words of 16 bits to sequential locations, assuming in both cases that all addresses are outside the write pro- tected area. after the start of the programming cy- cle, a busy/ready signal is available on serial data output (q) when chip select input (s) is driv- en high. figure 3. dip, so and tssop connections note: see package mechanical section for package dimen- sions, and how to identify pin-1. s chip select input d serial data input q serial data output c serial clock pre protection register enable w write enable v cc supply voltage v ss ground ai02020 d v cc m93sx6 v ss c q pre w s v ss q w pre c sv cc d ai02021 m93sx6 1 2 3 4 8 7 6 5
5/34 m93s66, m93s56, m93s46 an internal power-on data protection mechanism in the m93sx6 inhibits the device when the supply is too low. power-on data protection to prevent data corruption and inadvertent write operations during power-up, a power-on reset (por) circuit resets all internal programming cir- cuitry, and sets the device in the write disable mode. ? at power-up and power-down, the device must not be selected (that is, chip select input (s) must be driven low) until the supply voltage reaches the operating value v cc specified in table 5. to table 6. . ? when v cc reaches its valid level, the device is properly reset (in the write disable mode) and is ready to decode and execute incoming instructions. for the m93sx6 devices (5v range) the por threshold voltage is around 3v. for the m93sx6- w (3v range) and m93sx6-r (2v range) the por threshold voltage is around 1.5v. instructions the instruction set of the m93sx6 devices con- tains seven instructions, as summarized in table 2. to table 3. . each instruction consists of the fol- lowing parts, as shown in figure 4. : each instruction is preceded by a rising edge on chip select input (s) with serial clock (c) being held low. a start bit, which is the first ?1? read on serial data input (d) during the rising edge of serial clock (c). two op-code bits, read on serial data input (d) during the rising edge of serial clock (c). (some instructions also use the first two bits of the address to define the op-code). the address bits of the byte or word that is to be accessed. for the m93s46, the address is made up of 6 bits (see table 2. ). for the m93s56 and m93s66, the address is made up of 8 bits (see table 3. ). the m93sx6 devices are fabricated in cmos technology and are therefore able to run as slow as 0 hz (static input signals) or as fast as the max- imum ratings specified in table 16. to table 19. .
m93s66, m93s56, m93s46 6/34 table 2. instruction set for the m93s46 note: 1. x = don?t care bit. instruction description w pre start bit op- code address 1 data required clock cycles additional comments read read data from memory x 0 1 10 a5-a0 q15-q0 write write data to memory 1 0 1 01 a5-a0 d15-d0 25 write is executed if the address is not inside the protected area paw r i t e page write to memory 10 1 11 a5-a0 n x d15-d0 9 + n x 16 write is executed if all the n addresses are not inside the protected area wral write all memory with same data 10 1 0001 xxxxd15-d0 25 write all data if the protection register is cleared wen write enable 1 0 1 00 11 xxxx 9 wds write disable x 0 1 00 00 xxxx 9 prread protection register read x 1 1 10 xxxxxx q5-q0 + flag data output = protection register content + protection flag bit prwrite protection register write 11 1 01 a5-a0 9 data above specified address a5-a0 are protected prclear protection register clear 1 1 1 11 111111 9 protect flag is also cleared (cleared flag = 1) pren protection register enable 1 1 1 00 11xxxx 9 prds protection register disable 1 1 1 00 000000 9 otp bit is set permanently
7/34 m93s66, m93s56, m93s46 table 3. instruction set for the m93s66, m93s56 note: 1. x = don?t care bit. 2. address bit a7 is not decoded by the m93s56. instruction description w pre start bit op- code address 1,2 data required clock cycles additional comments read read data from memory x 0 1 10 a7-a0 q15-q0 write write data to memory 1 0 1 01 a7-a0 d15-d0 27 write is executed if the address is not inside the protected area paw r i t e page write to memory 10 1 11 a7-a0 n x d15-d0 11 + n x 16 write is executed if all the n addresses are not inside the protected area wral write all memory with same data 1 0 1 00 01xxxxxx d15-d0 27 write all data if the protection register is cleared wen write enable 1 0 1 00 11xxxxxx 11 wds write disable x 0 1 00 00xxxxxx 11 prread protection register read x 1 1 10 xxxxxxxx q7-q0 + flag data output = protection register content + protection flag bit prwrite protection register write 11 1 01 a7-a0 11 data above specified address a7-a0 are protected prclear protection register clear 1 1 1 11 11111111 11 protect flag is also cleared (cleared flag = 1) pren protection register enable 1 1 1 00 11xxxxxx 11 prds protection register disable 1 1 1 00 00000000 11 otp bit is set permanently
m93s66, m93s56, m93s46 8/34 figure 4. read, write, wen and wds sequences note: for the meanings of an, xn, qn and dn, see table 2. and table 3. . ai00889d 1 1 0 an a0 qn q0 data out d s q s write addr op code 1 0an a0 data in d q op code dn d0 1 busy ready s write enable 1 0xnx0 d op code 1 01 s write disable 1 0xnx0 d op code 0 0 0 check status addr pre read pre w pre w pre
9/34 m93s66, m93s56, m93s46 read the read data from memory (read) instruction outputs serial data on serial data output (q). when the instruction is received, the op-code and address are decoded, and the data from the mem- ory is transferred to an output shift register. a dum- my 0 bit is output first, followed by the 16-bit word, with the most significant bit first. output data changes are triggered by the rising edge of serial clock (c). the m93sx6 automatically increments the internal address register and clocks out the next byte (or word) as long as the chip select in- put (s) is held high. in this case, the dummy 0 bit is not output between bytes (or words) and a con- tinuous stream of data can be read. write enable and write disable the write enable (wen) instruction enables the future execution of write instructions, and the write disable (wds) instruction disables it. when power is first applied, the m93sx6 initializes itself so that write instructions are disabled. after an write en- able (wen) instruction has been executed, writing remains enabled until an write disable (wds) in- struction is executed, or until v cc falls below the power-on reset threshold voltage. to protect the memory contents from accidental corruption, it is advisable to issue the write disable (wds) in- struction after every write cycle. the read data from memory (read) instruction is not affected by the write enable (wen) or write disable (wds) instructions. write the write data to memory (write) instruction is composed of the start bit plus the op-code fol- lowed by the address and the 16 data bits to be written. write enable (w) must be held high before and during the instruction. input address and data, on serial data input (d) are sampled on the rising edge of serial clock (c). after the last data bit has been sampled, the chip select input (s) must be taken low before the next rising edge of serial clock (c). if chip select input (s) is brought low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. while the m93sx6 is performing a write cycle, but after a delay (t slsh ) before the status information becomes available, chip select input (s) can be driven high to monitor the status of the write cycle: serial data output (q) is driven low while the m93sx6 is still busy, and high when the cycle is complete, and the m93sx6 is ready to receive a new instruction. the m93sx6 ignores any data on the bus while it is busy on a write cycle. once the m93sx6 is ready, serial data output (q) is driven high, and remains in this state until a new start bit is decoded or the chip select input (s) is brought low. programming is internally self-timed, so the exter- nal serial clock (c) may be disconnected or left running after the start of a write cycle.
m93s66, m93s56, m93s46 10/34 figure 5. pawrite and wral sequence note: for the meanings of an, xn and dn, please see table 2. and table 3. . page write a page write to memory (pawrite) instruction contains the first address to be written, followed by up to 4 data words. after the receipt of each data word, bits a1-a0 of the internal address register are incremented, the high order bits remaining unchanged (a7-a2 for m93s66, m93s56; a5-a2 for m93s46). users must take care, in the software, to ensure that the last word address has the same upper order ad- dress bits as the initial address transmitted to avoid address roll-over. the page write to memory (pawrite) instruction will not be executed if any of the 4 words address- es the protected area. write enable (w) must be held high before and during the instruction. input address and data, on serial data input (d) are sampled on the rising edge of serial clock (c). after the last data bit has been sampled, the chip select input (s) must be taken low before the next rising edge of serial clock (c). if chip select input (s) is brought low before or after this specific time frame, the self-timed programming cycle will not ai00890c s page write 1 1an a0 data in d q op code dn d0 1 busy ready check status addr pre w s write all 1 0xnx0 data in d q op code dn d0 0 busy ready check status addr pre w 01
11/34 m93s66, m93s56, m93s46 be started, and the addressed location will not be programmed. while the m93sx6 is performing a write cycle, but after a delay (t slsh ) before the status information becomes available, chip select input (s) can be driven high to monitor the status of the write cycle: serial data output (q) is driven low while the m93sx6 is still busy, and high when the cycle is complete, and the m93sx6 is ready to receive a new instruction. the m93sx6 ignores any data on the bus while it is busy on a write cycle. once the m93sx6 is ready, serial data output (q) is driven high, and remains in this state until a new start bit is decoded or the chip select input (s) is brought low. programming is internally self-timed, so the exter- nal serial clock (c) may be disconnected or left running after the start of a write cycle. write all the write all memory with same data (wral) in- struction is valid only after the protection register has been cleared by executing a protection reg- ister clear (prclear) instruction. the write all memory with same data (wral) instruction simul- taneously writes the whole memory with the same data word given in the instruction. write enable (w) must be held high before and during the instruction. input address and data, on serial data input (d) are sampled on the rising edge of serial clock (c). after the last data bit has been sampled, the chip select input (s) must be taken low before the next rising edge of serial clock (c). if chip select input (s) is brought low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. while the m93sx6 is performing a write cycle, but after a delay (t slsh ) before the status information becomes available, chip select input (s) can be driven high to monitor the status of the write cycle: serial data output (q) is driven low while the m93sx6 is still busy, and high when the cycle is complete, and the m93sx6 is ready to receive a new instruction. the m93sx6 ignores any data on the bus while it is busy on a write cycle. once the m93sx6 is ready, serial data output (q) is driven high, and remains in this state until a new start bit is decoded or the chip select input (s) is brought low. programming is internally self-timed, so the exter- nal serial clock (c) may be disconnected or left running after the start of a write cycle.
m93s66, m93s56, m93s46 12/34 figure 6. pread, prwrite and pren sequences note: for the meanings of an, xn and dn, please see table 2. and table 3. . ai00891d 1 1 0 xn x0 data out d s q s protect register write addr op code 1 0an a0 d q op code 1 busy ready s protect register enable 1 0xnx0 d op code 1 01 check status addr pre protect register read pre w pre w an a0 f f = protect flag
13/34 m93s66, m93s56, m93s46 figure 7. prclear and prds sequences note: for the meanings of an, xn and dn, please see table 2. and table 3. . ai00892c s protect register clear 1 1 d q op code 1 busy ready check status addr pre w 111 s protect register disable 1 0 d q op code 0 busy ready check status addr pre w 000
m93s66, m93s56, m93s46 14/34 write protection and the protection register the protection register on the m93sx6 is used to adjust the amount of memory that is to be write protected. the write protected area extends from the address given in the protection register, up to the top address in the m93sx6 device. two flag bits are used to indicate the protection register status: ? protection flag: this is used to enable/disable protection of the write-protected area of the m93sx6 memory ? otp bit: when set, this disables access to the protection register, and thus prevents any further modifications to the value in the protection register. the lower-bound memory address is written to the protection register using the protection register write (prwrite) instruction. it can be read using the protection register read (prread) instruc- tion. the protection register enable (pren) instruc- tion must be executed before any prclear, prwrite or prds instruction, and with appropri- ate levels applied to the protection enable (pre) and write enable (w) signals. write-access to the protection register is achieved by executing the following sequence: ? execute the write enable (wen) instruction ? execute the protection register enable (pren) instruction ? execute one prwrite, prclear or prds instructions, to set a new boundary address in the protection register, to clear the protection address (to all 1s), or permanently to freeze the value held in the protection register. protection register read the protection register read (prread) instruc- tion outputs, on serial data output (q), the con- tent of the protection register, followed by the protection flag bit. the protection enable (pre) signal must be driven high before and during the instruction. as with the read data from memory (read) in- struction, a dummy 0 bit is output first. since it is not possible to distinguish between the protection register being cleared (all 1s) or having been writ- ten with all 1s, the user must check the protection flag status (and not the protection register con- tent) to ascertain the setting of the memory protec- tion. protection register enable the protection register enable (pren) instruc- tion is used to authorize the use of instructions that modify the protection register (prwrite, prclear, prds). the protection register en- able (pren) instruction does not modify the pro- tection flag bit value. note: a write enable (wen) instruction must be executed before the protection register enable (pren) instruction. both the protection enable (pre) and write enable (w) signals must be driv- en high during the instruction execution. protection register clear the protection register clear (prclear) in- struction clears the address stored in the protec- tion register to all 1s, so that none of the memory is write-protected by the protection register. how- ever, it should be noted that all the memory re- mains protected, in the normal way, using the write enable (wen) and write disable (wds) in- structions. the protection register clear (prclear) in- struction clears the protection flag to 1. both the protection enable (pre) and write enable (w) signals must be driven high during the instruction execution. note: a protection register enable (pren) in- struction must immediately precede the protection register clear (prclear) instruction. protection register write the protection register write (prwrite) instruc- tion is used to write an address into the protection register. this is the address of the first word to be protected. after the protection register write (prwrite) instruction has been executed, all memory locations equal to and above the speci- fied address are protected from writing. the protection flag bit is set to 0, and can be read with protection register read (prread) instruc- tion. both the protection enable (pre) and write enable (w) signals must be driven high during the instruction execution. note: a protection register enable (pren) in- struction must immediately precede the protection register write (prwrite) instruction, but it is not necessary to execute first a protection register clear (prclear). protection register disable the protection register disable (prds) instruc- tion sets the one time programmable (otp) bit. this instruction is a one time only instruction which latches the protection register content, this content is therefore unalterable in the future. both the protection enable (pre) and write enable (w) signals must be driven high during the instruction execution. the otp bit cannot be directly read, it can be checked by reading the content of the pro- tection register, using the protection register read (prread) instruction, then by writing this same value back into the protection register, us-
15/34 m93s66, m93s56, m93s46 ing the protection register write (prwrite) in- struction. when the otp bit is set, the ready/busy status cannot appear on serial data output (q). when the otp bit is not set, the busy status ap- pears on serial data output (q). note: a protection register enable (pren) in- struction must immediately precede the protection register disable (prds) instruction. common i/o operation serial data output (q) and serial data input (d) can be connected together, through a current lim- iting resistor, to form a common, single-wire data bus. some precautions must be taken when oper- ating the memory in this way, mostly to prevent a short circuit current from flowing when the last ad- dress bit (a0) clashes with the first data bit on se- rial data output (q). please see the application note an394 for details. figure 8. write sequence with one clock glitch clock pulse counter in a noisy environment, the number of pulses re- ceived on serial clock (c) may be greater than the number delivered by the bus master (the micro- controller). this can lead to a misalignment of the instruction of one or more bits (as shown in figure 8. ) and may lead to the writing of erroneous data at an erroneous address. to combat this problem, the m93sx6 has an on- chip counter that counts the clock pulses from the start bit until the falling edge of the chip select in- put (s). if the number of clock pulses received is not the number expected, the write, pawrite, wrall, prwrite or prclear instruction is aborted, and the contents of the memory are not modified. the number of clock cycles expected for each in- struction, and for each member of the m93sx6 family, are summarized in table 2. to table 3. . for example, a write data to memory (write) in- struction on the m93s56 (or m93s66) expects 27 clock cycles from the st art bit to t he fallin g edge of chip select input (s). that is: 1 start bit + 2 op-code bits + 8 address bits + 16 data bits ai01395 s an-1 c d write start d0 "1" "0" an glitch an-2 address and data are shifted by one bit
m93s66, m93s56, m93s46 16/34 maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 4. absolute maximum ratings note: 1. compliant with jedec std j-std-020b (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 ? , r2=500 ? ) symbol parameter min. max. unit t stg storage temperature ?65 150 c t lead lead temperature during soldering see note 1 c v out output range (q = v oh or hi-z) ?0.50 v cc +0.5 v v in input range ?0.50 v cc +1 v v cc supply voltage ?0.50 6.5 v v esd electrostatic discharge voltage (human body model) 2 ?4000 4000 v
17/34 m93s66, m93s56, m93s46 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 5. operating conditions (m93sx6) table 6. operating conditions (m93sx6-w) table 7. operating conditions (m93sx6-r) table 8. ac measurement conditions (m93sx6) note: output hi-z is defined as the point where data out is no longer driven. table 9. ac measurement conditions (m93sx6-w and m93sx6-r) note: output hi-z is defined as the point where data out is no longer driven. symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v t a ambient operating temperature (device grade 6) ?40 85 c ambient operating temperature (device grade 3) ?40 125 c symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature (device grade 6) ?40 85 c symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature (device grade 6) ?40 85 c symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input pulse voltages 0.4 v to 2.4 v v input timing reference voltages 1.0 v and 2.0 v v output timing reference voltages 0.8 v and 2.0 v v symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc v input timing reference voltages 0.3v cc to 0.7v cc v output timing reference voltages 0.3v cc to 0.7v cc v
m93s66, m93s56, m93s46 18/34 figure 9. ac testing input output waveforms table 10. capacitance note: sampled only, not 100% tested, at t a =25c and a frequency of 1 mhz. symbol parameter test condition min max unit c out output capacitance v out = 0v 5pf c in input capacitance v in = 0v 5pf ai02791 2.4v 0.4v 2.0v 0.8v 2v 1v input output 0.8v cc 0.2v cc 0.7v cc 0.3v cc m93sxx-w & m93sxx-r m93sxx
19/34 m93s66, m93s56, m93s46 table 11. dc characteristics (m93sx6, device grade 6) note: 1. current product: identified by process identification letter f or m. 2. new product: identified by process identification letter w or g. table 12. dc characteristics (m93sx6, device grade 3) note: 1. current product: identified by process identification letter f or m. 2. new product: identified by process identification letter w or g. symbol parameter test condition min. max. unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current v cc = 5v, s = v ih , f = 1 mhz, current product 1 1.5 ma v cc = 5v, s = v ih , f = 2 mhz, new product 2 2 ma i cc1 supply current (stand-by) v cc = 5v, s = v ss , c = v ss , current product 1 50 a v cc = 5v, s = v ss , c = v ss , new product 2 15 a v il input low voltage v cc = 5v 10% ?0.45 0.8 v v ih input high voltage v cc = 5v 10% 2 v cc + 1 v v ol output low voltage v cc = 5v, i ol = 2.1ma 0.4 v v oh output high voltage v cc = 5v, i oh = ?400a 2.4 v symbol parameter test condition min. max. unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current v cc = 5v, s = v ih , f = 1 mhz, current product 1 1.5 ma v cc = 5v, s = v ih , f = 2 mhz, new product 2 2 ma i cc1 supply current (stand-by) v cc = 5v, s = v ss , c = v ss , current product 1 50 a v cc = 5v, s = v ss , c = v ss , new product 2 15 a v il input low voltage v cc = 5v 10% ?0.45 0.8 v v ih input high voltage v cc = 5v 10% 2 v cc + 1 v v ol output low voltage v cc = 5v, i ol = 2.1ma 0.4 v v oh output high voltage v cc = 5v, i oh = ?400a 2.4 v
m93s66, m93s56, m93s46 20/34 table 13. dc characteristics (m93sx6-w, device grade 6) note: 1. current product: identified by process identification letter f or m. 2. new product: identified by process identification letter w or g. symbol parameter test condition min. max. unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current (cmos inputs) v cc = 5v, s = v ih , f = 1 mhz, current product 1 1.5 ma v cc = 2.5v, s = v ih , f = 1 mhz, current product 1 1 ma v cc = 5v, s = v ih , f = 2 mhz, new product 2 2 ma v cc = 2.5v, s = v ih , f = 2 mhz, new product 2 1 ma i cc1 supply current (stand-by) v cc = 2.5v, s = v ss , c = v ss , current product 1 10 a v cc = 2.5v, s = v ss , c = v ss , new product 2 5 a v il input low voltage (d, c, s) ?0.45 0.2 v cc v v ih input high voltage (d, c, s) 0.7 v cc v cc + 1 v v ol output low voltage (q) v cc = 5v, i ol = 2.1ma 0.4 v v cc = 2.5v, i ol = 100a 0.2 v v oh output high voltage (q) v cc = 5v, i oh = ?400a 2.4 v v cc = 2.5v, i oh = ?100a v cc ?0.2 v
21/34 m93s66, m93s56, m93s46 table 14. dc characteristics (m93sx6-w, device grade 3) note: 1. new product: identified by process identification letter w or g. table 15. dc characteristics (m93sx6-r) note: 1. preliminary data: this product is under development. for more infomation, please contact your nearest st sales office. symbol parameter test condition min 1 .max. 1 unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current (cmos inputs) v cc = 5v, s = v ih , f = 2 mhz 2 ma v cc = 2.5v, s = v ih , f = 2 mhz 1 ma i cc1 supply current (stand-by) v cc = 2.5v, s = v ss , c = v ss 5 a v il input low voltage (d, c, s) ?0.45 0.2 v cc v v ih input high voltage (d, c, s) 0.7 v cc v cc + 1 v v ol output low voltage (q) v cc = 5v, i ol = 2.1ma 0.4 v v cc = 2.5v, i ol = 100a 0.2 v v oh output high voltage (q) v cc = 5v, i oh = ?400a 2.4 v v cc = 2.5v, i oh = ?100a v cc ?0.2 v symbol parameter test condition min. 1 max. 1 unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current (cmos inputs) v cc = 5v, s = v ih , f = 2 mhz 2 ma v cc = 1.8v, s = v ih , f = 1 mhz 1 ma i cc1 supply current (stand-by) v cc = 1.8v, s = v ss , c = v ss 2 a v il input low voltage (d, c, s) ?0.45 0.2 v cc v v ih input high voltage (d, c, s) 0.8 v cc v cc + 1 v v ol output low voltage (q) v cc = 1.8v, i ol = 100a 0.2 v v oh output high voltage (q) v cc = 1.8v, i oh = ?100a v cc ?0.2 v
m93s66, m93s56, m93s46 22/34 table 16. ac characteristics (m93sx6, device grade 6 or 3) note: 1. t chcl + t clch 1 / f c . 2. chip select input (s) must be brought low for a minimum of tslsh between consecutive instruction cycles. 3. current product: identified by process identification letter f or m. 4. new product: identified by process identification letter w or g. test conditions specified in table 8. and table 5. symbol alt. parameter min. 3 max. 3 min. 4 max. 4 unit f c f sk clock frequency d.c. 1 d.c. 2 mhz t prvch t pres protect enable valid to clock high 50 50 ns t wvch t pes write enable valid to clock high 50 50 ns t clprx t preh clock low to protect enable transition 0 0 ns t slwx t peh chip select low to write enable transition 250 250 ns t slch chip select low to clock high 250 50 ns t shch t css chip select set-up time m93c46, m93c56, m93c66 50 50 ns chip select set-up time m93c76, m93c86 100 50 ns t slsh 2 t cs chip select low to chip select high 250 200 ns t chcl 1 t skh clock high time 250 200 ns t clch 1 t skl clock low time 250 200 ns t dvch t dis data in set-up time 100 50 ns t chdx t dih data in hold time 100 50 ns t clsh t sks clock set-up time (relative to s) 100 50 ns t clsl t csh chip select hold time 0 0 ns t shqv t sv chip select to ready/busy status 400 200 ns t slqz t df chip select low to output hi-z 200 100 ns t chql t pd0 delay to output low 400 200 ns t chqv t pd1 delay to output valid 400 200 ns t w t wp erase/write cycle time 10 5 ms
23/34 m93s66, m93s56, m93s46 table 17. ac characteristics (m93sx6-w, device grade 6) note: 1. t chcl + t clch 1 / f c . 2. chip select input (s) must be brought low for a minimum of tslsh between consecutive instruction cycles. 3. current product: identified by process identification letter f or m. 4. new product: identified by process identification letter w or g. test conditions specified in table 9. and table 6. symbol alt. parameter min. 3 max. 3 min. 4 max. 4 unit f c f sk clock frequency d.c. 1 d.c. 2 mhz t prvch t pres protect enable valid to clock high 50 50 ns t wvch t pes write enable valid to clock high 50 50 ns t clprx t preh clock low to protect enable transition 0 0 ns t slwx t peh chip select low to write enable transition 250 250 ns t slch chip select low to clock high 250 50 ns t shch t css chip select set-up time 100 50 ns t slsh 2 t cs chip select low to chip select high 1000 200 ns t chcl 1 t skh clock high time 350 200 ns t clch 1 t skl clock low time 250 200 ns t dvch t dis data in set-up time 100 50 ns t chdx t dih data in hold time 100 50 ns t clsh t sks clock set-up time (relative to s) 100 50 ns t clsl t csh chip select hold time 0 0 ns t shqv t sv chip select to ready/busy status 400 200 ns t slqz t df chip select low to output hi-z 200 100 ns t chql t pd0 delay to output low 400 200 ns t chqv t pd1 delay to output valid 400 200 ns t w t wp erase/write cycle time 10 5 ms
m93s66, m93s56, m93s46 24/34 table 18. ac characteristics (m93sx6-w, device grade 3) note: 1. t chcl + t clch 1 / f c . 2. chip select input (s) must be brought low for a minimum of tslsh between consecutive instruction cycles. 3. new product: identified by process identification letter w or g. test conditions specified in table 9. and table 6. symbol alt. parameter min. 3 max. 3 unit f c f sk clock frequency d.c. 2 mhz t prvch t pres protect enable valid to clock high 50 ns t wvch t pes write enable valid to clock high 50 ns t clprx t preh clock low to protect enable transition 0 ns t slwx t peh chip select low to write enable transition 250 ns t slch chip select low to clock high 50 ns t shch t css chip select set-up time 50 ns t slsh 2 t cs chip select low to chip select high 200 ns t chcl 1 t skh clock high time 200 ns t clch 1 t skl clock low time 200 ns t dvch t dis data in set-up time 50 ns t chdx t dih data in hold time 50 ns t clsh t sks clock set-up time (relative to s) 50 ns t clsl t csh chip select hold time 0 ns t shqv t sv chip select to ready/busy status 200 ns t slqz t df chip select low to output hi-z 100 ns t chql t pd0 delay to output low 200 ns t chqv t pd1 delay to output valid 200 ns t w t wp erase/write cycle time 5 ms
25/34 m93s66, m93s56, m93s46 table 19. ac characteristics (m93sx6-r) note: 1. t chcl + t clch 1 / f c . 2. chip select input (s) must be brought low for a minimum of tslsh between consecutive instruction cycles. 3. preliminary data: this product is under development. for more infomation, please contact your nearest st sales office. test conditions specified in table 9. and table 7. symbol alt. parameter min. 3 max. 3 unit f c f sk clock frequency d.c. 1 mhz t prvch t pres protect enable valid to clock high 50 ns t wvch t pes write enable valid to clock high 50 ns t clprx t preh clock low to protect enable transition 0 ns t slwx t peh chip select low to write enable transition 250 ns t slch chip select low to clock high 250 ns t shch t css chip select set-up time 50 ns t slsh 2 t cs chip select low to chip select high 250 ns t chcl 1 t skh clock high time 250 ns t clch 1 t skl clock low time 250 ns t dvch t dis data in set-up time 100 ns t chdx t dih data in hold time 100 ns t clsh t sks clock set-up time (relative to s) 100 ns t clsl t csh chip select hold time 0 ns t shqv t sv chip select to ready/busy status 400 ns t slqz t df chip select low to output hi-z 200 ns t chql t pd0 delay to output low 400 ns t chqv t pd1 delay to output valid 400 ns t w t wp erase/write cycle time 10 ms
m93s66, m93s56, m93s46 26/34 figure 10. synchronous timing (start and op-code input) figure 11. synchronous timing (read or write) pre w c s d op code op code start start op code input tchdx tdvch tclsh tclch tchcl twvch tprvch ai02025 tshch ai002026 c d q address input hi-z tdvch tclsl a0 s data output tchqv tchdx tchql an tslsh tslqz q15 q0
27/34 m93s66, m93s56, m93s46 figure 12. synchronous timing (read or write) pre w c s d hi-z tw tdvch ai02027 q tclprx tslwx tclsl tchdx tslsh tslqz busy tshqv ready write cycle address/data input an a0/d0 tslch
m93s66, m93s56, m93s46 28/34 package mechanical figure 13. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package outline note: drawing is not to scale. table 20. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package mechanical data symb. mm inches typ. min. max. typ. min. max. a 5.33 0.210 a1 0.38 0.015 a2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 d 9.27 9.02 10.16 0.365 0.355 0.400 e 7.87 7.62 8.26 0.310 0.300 0.325 e1 6.35 6.10 7.11 0.250 0.240 0.280 e2.54??0.100?? ea 7.62 ? ? 0.300 ? ? eb 10.92 0.430 l 3.30 2.92 3.81 0.130 0.115 0.150 pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e
29/34 m93s66, m93s56, m93s46 figure 14. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline note: drawing is not to scale. table 21. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e1.27??0.050?? h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 0 8 0 8 n8 8 cp 0.10 0.004 so-a e n cp b e a d c l a1 1 h h x 45?
m93s66, m93s56, m93s46 30/34 figure 15. tssop8 3x3mm2 ? 8 lead thin shrink small outline, 3x3mm2 body size, package outline note: drawing is not to scale. table 22. tssop8 3x3mm2 ? 8 lead thin shrink small outline, 3x3mm2 body size, mechanical data symbol mm inches typ. min. max. typ. min. max. a 1.100 0.0433 a1 0.050 0.150 0.0020 0.0059 a2 0.850 0.750 0.950 0.0335 0.0295 0.0374 b 0.250 0.400 0.0098 0.0157 c 0.130 0.230 0.0051 0.0091 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 4.900 4.650 5.150 0.1929 0.1831 0.2028 e1 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? cp 0.100 0.0039 l 0.550 0.400 0.700 0.0217 0.0157 0.0276 l1 0.950 0.0374 0 6 0 6 tssop8bm 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
31/34 m93s66, m93s56, m93s46 figure 16. tssop8 ? 8 lead thin shrink small outline, package outline note: drawing is not to scale. table 23. tssop8 ? 8 lead thin shrink small outline, package mechanical data symbol mm inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 0 8 0 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
m93s66, m93s56, m93s46 32/34 part numbering table 24. ordering information scheme note: 1. st strongly recommends the use of the automotive grade devices for use in an automotive environment. the high reliabilit y cer- tified flow (hrcf) is described in the quality note qnee9801. please ask your nearest st sales office for a copy. 2. available only on new products: identified by the process identification letter w or g. devices are shipped from the factory with the memory content set at all 1s (ffh). for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales of- fice. table 25. how to identify current and new products by the process identification letter note: 1. this example comes from the s08 package. other packages have similar information. for further information, please ask yo ur st sales office for process change notice pcn mpg/ee/0059 (pcee0059). example: m93s66 ? w mn 6 t p device type m93 = microwire serial access eeprom (x16) with block protection device function 66 = 4 kbit (256 x 16) 56 = 2 kbit (128 x 16) 46 = 1 kbit (64 x 16) operating voltage blank = v cc = 4.5 to 5.5v w = v cc = 2.5 to 5.5v r = v cc = 1.8 to 5.5v package bn = pdip8 mn = so8 (150 mil width) dw = tssop8 (169 mil width) ds 2 = tssop8 (3x3mm body size) device grade 6 = industrial: device tested with standard test flow over ?40 to 85 c 3 = automotive: device tested with high reliability certified flow 1 over ?40 to 125 c option blank = standard packing t = tape & reel packing plating technology blank = standard snpb plating p = lead-free and rohs compliant g = lead-free, rohs compliant, sb 2 o 3 -free and tbba-free markings on current products 1 markings on new products 1 m93s46w6 ayww f (or ayww m ) m93s46w6 ay w w w (or ayww g )
33/34 m93s66, m93s56, m93s46 revision history table 26. document revision history date rev. description of revision 07-mar-2002 2.0 document reformatted, and reworded, using the new template. temperature range 1 removed. tssop8 (3x3mm) package added. new products, identified by the process letter w, added, with fc(max) increased to 1mhz for -r voltage range, and to 2mhz for all other ranges (and corresponding parameters adjusted). 26-mar-2003 2.1 value of standby current (max) corrected in dc characteristics tables for -w and -r ranges v out and v in separated from v io in the absolute maximum ratings table 14-apr-2003 2.2 values corrected in ac characteristics tables for -w range (tslsh, tdvch, tclsl) for devices with process identification letter w. 23-may-2003 2.3 standby current corrected for -r range. four missing parameters restored to all ac characteristics tables 24-nov-2003 3.0 table of contents, and pb-free options added. v il (min) improved to -0.45v. 19-apr-2004 4.0 absolute maximum ratings for v io (min) and v cc (min) changed. soldering temperature information clarified for rohs compliant devices. device grade 3 clarified, with reference to hrcf and automotive environments. process identification letter ?g? information added
m93s66, m93s56, m93s46 34/34 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com
about st products applications support buy news & events st worldwide contact us login search the site part number search search for part #: m93s56-wmn3tp/s example: *74*00* matching documents: 1 - 1 of 1 generic part number(s) orderable part number(s) status product page/ datasheet description m93s56 - w m93s56 - wmn3tp/s active 4kbit, 2kbit and 1kbit (16-bit wide) microwire serial access eeprom with block protection memories | eeprom, serial | serial eeprom, microwire bus, m93 search time: 0.09s all rights reserved ? 2007 stmicroelectronics :: terms of use :: privacy policy pa g e 1 of 1 stmicroelectronics | part number search 27-au g -2007 mhtml:file://c:\temp\sgs t\m93s56-wmn3tp%20s.mht

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